The circuits for detecting a logic transition (Logic Transition Detection, or LTD) are well known; those circuits generate a pulse-type detection signal in response to a transition of a logic signal (both with a leading edge from the logic value 0 to the logic value 1 and with a trailing edge from the logic value 1 to the logic value 0).
The LTD circuits commonly find application in devices that must be able to react to any switching of the logic signal (irrespectively of the type of edge of the transition). For example, the LTD circuits are used in an asynchronous memory device for enabling a reading operation following a switching of an input address; in this case, they are also known as Address Transition Detection (ATD) circuits.
Different structures have been proposed for implementing the LTD circuits. A known solution consists of applying the logic signal to a delay line. The logic signal so delayed is then compared with the original logic signal. When these two signals are equal, the detection signal is deasserted; conversely, the detection signal is asserted. In this way, each transition of the logic signal generates a pulse having a length equal to the introduced delay.
A drawback of the structure described above consists of the fact that it is very difficult to make delay lines that are accurate and with steady characteristics (for example, as a power supply voltage of the LTD circuit or its operating temperature change). Therefore, it is not possible to control the length of the detection signal pulse accurately.
A different solution known in the art provides the use of two capacitors, which are controlled by the logic signal and by its inverted value, respectively; the signals generated by the two capacitors are then compared. In a steady condition, the voltage at a capacitor is equal to a power supply voltage while the voltage at the other capacitor is equal to a reference voltage (or ground); as a consequence, the detection signal is deasserted. At each switching of the logic signal, the capacitor at the power supply voltage is discharged to ground and the capacitor at ground is charged to the power supply voltage (through respective MOS transistors); the circuit is dimensioned so that the charging time is always higher than the discharging time. As a consequence, the detection signal is asserted during the time interval in which both the signals generated by the two capacitors are lower than a preset threshold voltage.
However, the operation of this circuit is strongly dependent on its operative conditions as well. Particularly, an increase of the power supply voltage and/or a decrease of the temperature raise the conductivity of the MOS transistors, thereby reducing the length of the discharging and charging times of the capacitors; however, such reduction is almost imperceptible for the discharging (very fast). The decrease of the temperature also lowers the threshold voltage. It follows that the length of the detection signal pulse shortens as the power supply voltage increases and the temperature decreases.
Such variability of the length of the detection signal pulse is very harmful. For example, in a memory device the ATD circuit should be dimensioned so as to ensure a length of the pulse that guarantees the enabling of the reading operation in the worse operative condition of the circuit; therefore, in a standard operative condition the length of the pulse is higher than it is necessary, thereby increasing a reading access time of the memory device.